// -*- mode:c++ -*-
//
// 2009-2010 HIT Microelectronic Center all rights reserved
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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//
// Date: Dec. 2009
// Authors: Gou Pengfei


def operand_types {{
    'sb' : ('signed int', 8),
    'ub' : ('unsigned int', 8),
    'sh' : ('signed int', 16),
    'uh' : ('unsigned int', 16),
    'sw' : ('signed int', 32),
    'uw' : ('unsigned int', 32),
    'sd' : ('signed int', 64),
    'ud' : ('unsigned int', 64),
    'sf' : ('float', 32),
    'df' : ('float', 64),
}};

// Operands of TRIPS ISA are explicitly embedded into the EDGEStaticInst class.
// As a result, they ought to be read from EDGEStaticInst rather than from regs.
// An exceptin of operand is Global read/write instrutions of TRIPS ISA which 
// operate the global registers between Hyperblocks.
def operands {{

    'Gr_w': ('IntReg', 'ud', 'GR_W', 'IsInteger', 1),
    'Gr_r': ('IntReg', 'ud', 'GR_R', 'IsInteger', 1 ),

    'Op0': ('IntIQ', 'ud', '0', 'IsInteger', 1),
    'Op1': ('IntIQ', 'ud', '1', 'IsInteger', 2),
    
    'FOp0': ('FloatIQ', 'df', '0', 'IsFloating', 1),
    'FOp1': ('FloatIQ', 'df', '1', 'IsFloating', 2),

    'RESULT': ('IntIQ', 'ud', None, 'IsInteger', 1),
    'FRESULT': ('FloatIQ', 'df', None, 'IsFloating', 1),

    'Mem':('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 1),
    'NPC':('NPC', 'ud', None, 'IsControl', 1),
    'NextBlockPC': ('NextBlockPC', 'ud', None, 'IsControl', 1),

    'R0':('IntReg', 'ud', '0', 'IsInteger', 1), 
}};

